We are looking for an experienced Design Verification Engineer (Contract) to join our team and support ongoing PCIe verification efforts. This role involves hands-on test bench development, debugging, and compliance-focused verification using Avery PCIe VIP.
📌 Responsibilities
· Develop, enhance, and maintain SystemVerilog/UVM testbenches
· Create directed, random, and compliance-driven test scenarios
· Integrate and work extensively with Avery PCIe VIP
· Debug simulation failures and analyze PCIe protocol violations
· Contribute to coverage closure and verification signoff
📌 Required Qualifications
· 5+ years of experience in Design Verification
· Strong proficiency in SystemVerilog and UVM
· Hands-on experience using Avery PCIe VIP (mandatory)
· Solid understanding of the PCIe protocol (Gen6 preferred)
📌 Nice-to-Have
· Experience with Avery Compliance test suite
· Familiarity with PCIe Physical and Data link layer protocol
· Knowledge of Root complex and Endpoint
· Understanding of scoreboards, monitors, and verification architecture design
📌 Contract Details
· Location: Remote / On-site (Preferred)
· Start date: Immediate
· Hourly/weekly rate: DOE (Depending on Experience)
Top Skills
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