Own Jenkins-based RTL quality and release-promotion pipelines across lint, CDC, RDC, synthesis, and STA. Build QoR tracking, automated quality gates, waiver management, and evidence generation. Develop LLM-driven tooling to triage violations, create annotated pull requests, check spec-to-RTL consistency, and generate documentation. The role requires strong Python, hardware-flow knowledge, CI/CD expertise, and practical LLM integration experience. It is fully onsite Monday through Friday in the Bay Area, Vancouver, or Toronto.
Lint / CDC / Synthesis Quality -- AI-Augmented Design Flows - CI/CD for RTL
On-Site Monday-Friday - Bay Area, CA / Vancouver, BC / Toronto, ON
Full-Time - Equity Participation - Comprehensive Benefits
Eliyan is the chiplet interconnect pioneer behind NuLink, the industry's most efficient chiplet-to-chiplet PHY technology. With Series C funding from leading hyperscalers and AI infrastructure providers, we are scaling our digital design organization to support multiple concurrent IP programs across advanced process nodes.
Here is the honest version of this job. Our digital designers spend part of every week doing work a machine should be doing: re-running lint and CDC by hand, reading thousands of violations to find the twenty that matter, chasing down which synthesis run regressed QoR, and manually assembling the evidence that a branch is clean enough to promote to release.
We are looking for an engineer who can own the intersection of design quality and design automation. In this role you will define and enforce signoff criteria for lint, CDC, and synthesis across all active programs, build the waiver management and tracking infrastructure, and develop AI-augmented tooling that turns thousands of tool violations into actionable, designer-ready reviews. You will report into the digital design team and work directly alongside RTL designers — this is not a pure DevOps or IT role.
- Define and maintain lint, CDC, and synthesis elaboration signoff criteria across all active design programs.
- Build and own the waiver management system — structured flow with owner attribution, justification, expiration, and audit trail.
- Analyze synthesis results for area, timing, and power regressions; trace QoR anomalies to specific RTL changes.
- Collaborate with project design leads to develop and maintain project-specific rule decks, synthesis constraints, and signoff checklists.
- Own the Jenkins-based CI pipeline for RTL quality: lint, CDC, RDC, elaboration, synthesis, and STA.
- Build the dev-to-release promotion pipeline with automated gating, clean-run qualification, and handoff evidence generation.
- Develop per-project dashboards for QoR tracking, regression visibility, and release readiness.
- Develop LLM-based violation triage pipelines that classify lint and CDC output, suppress known-benign patterns, and surface real issues with context.
- Build automated pull requests with violations pre-filtered, grouped, and annotated for designer review.
- Implement spec-to-RTL consistency checking and CI-integrated documentation generation using LLM-driven pipelines.
- Benchmark AI output quality, measure false-negative rates, and establish guardrails the design team can trust.
KEY RESPONSIBILITIES
Design Quality & Signoff
Flow Automation and CIC
AI-Augmented Tooling
- BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 3+ years in ASIC or SoC design automation, with hands-on experience running and analyzing lint, CDC, or synthesis tools.
- Working knowledge of SystemVerilog and the RTL front-end flow — able to read violations, assess severity, and disposition findings.
- Proficiency in Python, Tcl, shell scripting, Git, Linux, and Makefiles.
- Experience building and maintaining CI/CD pipelines (Jenkins, GitLab CI, or GitHub Actions).
- Practical experience with LLM APIs or agent frameworks (e.g., Anthropic Claude, OpenAI) applied in a production or team-facing context.
- Authorization to work in the United States or Canada; visa sponsorship may be considered for exceptional candidates.
- On-site Monday through Friday at our Bay Area, Vancouver, or Toronto office.
WHAT YOU'LL BRING
- Experience with industry-standard EDA tools such as Synopsys SpyGlass, Design Compiler, PrimeTime; Cadence Genus, Conformal; or Siemens Questa.
- Experience building waiver management systems, violation databases, or design quality dashboards.
- Background in data engineering or ML systems: evaluation harnesses, retrieval pipelines, or production inference.
- Exposure to PHY, SerDes, die-to-die interconnect, or chiplet-based SoC design.
- Open-source contributions to design automation, hardware verification, or developer tooling.
PREFERRED QUALIFICATIONS
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