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Artificial Intelligence • Cloud • Machine Learning • Mobile • Software • Virtual Reality • App development
Own QA for micro-display software, firmware, and tools: develop test plans and test code, set up board-level test environments, collaborate with software and EE teams, log and document bugs in Jira, contribute to code reviews and tools UI documentation.
Top Skills:
ArmCC#C++CopilotCursorDisplayportHdmiI2CI3CJIRALogic AnalyzerMipiOscilloscopePciePythonRisc-VRtosSpiSwdUartUsb
Artificial Intelligence • Cloud • Machine Learning • Mobile • Software • Virtual Reality • App development
Develop and execute UVM/SystemVerilog-based verification for AR display integrated circuits. Build assertion-based testbenches, create and run verification plans with functional and code coverage, use Siemens Questa for simulation and debug, and automate verification flows while collaborating with digital, analog, software, and verification teams.
Top Skills:
AmbaAsicAssertion-Based TestbenchesCode CoverageEmbedded MicrocontrollerEmulationFunctional CoverageI2CLinuxMakeMipiPerlPythonRtlShellSiemens QuestaSpiSystemverilogTclUvmVerilog
Machine Learning • Payments • Security • Software • Financial Services
Lead and oversee high-complexity portfolios (often >$70M), manage strategic initiative governance, budgeting, milestone reporting, vendor relationships, and mentor other portfolio managers while coordinating across multidisciplinary teams to ensure portfolio success.
We’re looking for a senior-level Hardware Design Engineer to take the lead on complex ASIC and FPGA development projects. This role blends architecture design, hands-on implementation, and technical leadership. You’ll collaborate across engineering teams to deliver high-performance, reliable silicon solutions in a flexible hybrid environment.
Responsibilities
- Define HW architecture and evaluate design trade-offs for performance, area, and power.
- Lead RTL development, integration, and verification throughout the design cycle.
- Partner with firmware and verification teams to ensure top-quality silicon delivery.
- Mentor and review junior engineers’ work, promoting best practices and technical excellence.
- Provide design-in and bring-up support, including technical expertise for customer-facing projects.
Qualifications
- Strong command of SystemVerilog for RTL design and digital architecture.
- Experience using simulation tools such as Questa, Incisive, or VCS.
- Skilled in scripting (Python, Perl, Tcl) for automation and workflow optimization.
- Proven experience in ASIC or FPGA design, synthesis, and timing closure.
- Strong analytical thinking and communication skills, with the ability to manage complex priorities.
- 10+ years of relevant experience and a BSEE or MSEE degree.
Preferred / Plus
- Expertise in ASIC synthesis, timing constraints, CDC/RDC methodologies.
- Familiarity with UVM-based verification environments.
- Experience with high-speed memory technologies (HBM, GDDR, LPDDR, DDR).
- Understanding of AMBA AXI or CHI protocols.
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