SR Layout Engineer, DEG

Our vision is to transform how the world uses information to enrich life for all .
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Our DRAM Engineering Group drives the physical implementation behind Micron's most advanced memory products. We work across global sites and thrive on collaboration, problem-solving, and pushing technical boundaries.
We're looking for a Layout Engineer who will play a key role in building high-quality physical designs for our DRAM technologies. As an IP layout engineer, you will work with a dedicated and passionate core team. You will collaborate with peer teams across Micron's global footprint. This role involves managing multiple projects. Your work will directly influence product success and team workflows across Micron's global engineering community.
Responsibilities:

• Responsible for Design and development of IP layouts used in DRAM chips.
• Perform layout verification like LVS/DRC/EM, quality check and documentation.
• Responsible for on-time delivery of block-level layouts with acceptable quality.
• Guide and lead team-members in their execution of Sub block-level layouts & review their work.
• Contribute to effective project-management.
• Effectively communicate with engineering teams in US, India, Japan and other global teams to assure the success of the layout project.

Minimum Qualifications:

• Experience performing physical layout using Cadence Virtuoso or similar tools
• Familiarity with DRC, LVS, physical verification, and reliability checks
• Good understanding of Circuit Design principles and ability to come up with a high-performance layout that are optimal in area
• Should have hands on experience of Critical Analog Layout design of blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator and Differential Amplifier etc.,
• Good understanding of Analog Layout fundamentals (e.g. Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.)

Preferred Qualifications:

• Experience with DRAM, memory circuits, or large-scale hierarchical designs
• Background in parasitic extraction flows and post-layout optimization
• Hands-on experience with partial custom layout (devices, small analog blocks)
• Strong communication skills supporting global engineering collaboration

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits .
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
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