Teams at Fresh Consulting

Performs ASIC power analysis, physical design, and PPA optimization across RTL, gate-level, synthesis, physical design, timing, and power flows. Builds activity inputs, correlates power estimates, identifies power contributors, evaluates reduction strategies, and supports low-power UPF implementation. Automates analysis and reporting using TCL, Python, Make, and CI systems while debugging ASIC flows and communicating findings to design teams.