Teams at Quadric

Own customer technical evaluations through design wins by porting and optimizing workloads on Quadric’s Chimera GPNPU. Responsibilities include profiling performance, writing custom kernels, supporting quantization and compiler tooling, debugging with customer engineering teams, and guiding model architecture tradeoffs. The role also develops reusable SDK skills, porting playbooks, benchmark applications, and agentic FDE workflows while relaying customer feedback to engineering and product teams.

Own the full semiconductor IP licensing cycle across North America, from prospecting and technical evaluation through negotiation, closing, and account expansion. Build relationships with SoC and system companies, manage complex multi-stakeholder sales cycles, coordinate benchmarks with field engineers, negotiate license and royalty terms, maintain Salesforce forecasts, and achieve bookings targets. The role requires deep semiconductor IP expertise, technical fluency in NPU and SoC architecture, established industry relationships, and travel of approximately 30%.

Design and optimize deep learning compiler infrastructure for Quadric’s edge AI processor. Develop MLIR, TVM, and LLVM optimization passes, lower models from PyTorch, TensorFlow, and ONNX, implement graph transformations and quantization, optimize latency and memory usage, and collaborate on hardware-software co-design. The role also involves compiler validation, simulator development, FPGA/ASIC bring-up, and supporting advanced Transformer and vision models.