Senior ASIC Layout Engineer

We develop the foundation IP behind the Cisco Silicon One platform, which powers the world's most advanced switches and routers. Our international team delivers the standard cell libraries and analog IP that Silicon One ASICs are built on, on groundbreaking process technology.

We are hiring an ASIC Engineer to own standard cell layout for our next-generation ASICs on innovative FinFET and GAA nodes. You will design and verify high-performance cells, drive physical verification to clean signoff, and own library quality from GDS to release. You will work closely with circuit design, characterization, physical design and foundry teams. As the senior technical owner, you will set direction, define methodology and mentor engineers on the team.

• Drive the layout architecture and design of standard cell libraries: logic, high-drive, clock, level shifter, tap/boundary and specialty cells.
• Own the physical design of complex cells, optimizing for density, performance, power, EM and manufacturability.
• Drive physical verification to clean signoff: DRC, LVS, antenna, ERC, extraction and EM/IR.
• Define and own library QA: keep GDS, LEF, Liberty, NDM, CDL and Verilog consistent and ready for signoff.
• Develop and deploy automation for layout, verification and QA (Python, Tcl, SKILL).
• Contribute to analog/mixed-signal IP design and layout alongside the mixed-signal team.
• Work with the characterization team on extraction, netlist QA and correlation; contribute to library release.
• Lead block-level issue resolution and take part in chip-level debug with the physical design and STA teams.
• Drive layout and QA reviews, flag concerns early, and mentor engineers.

• Bachelor's + 7 years, Master's + 4 years, or PhD + 1 year of related experience in Electrical Engineering, Computer Engineering or a related field.
• First hand standard cell layout experience on advanced nodes such as TSMC 5nm, 3nm or 2nm.
• Strong physical verification and extraction experience, with tools such as Calibre, ICV, StarRC or Quantus.
• Experience with library QA and view consistency checks (GDS, LEF, Liberty, CDL).
• Proficiency in Cadence Virtuoso.

• Analog/mixed-signal design and layout experience, such as PLLs, LDOs, bandgaps, IOs or sensors, including matching, shielding and post-layout simulation.
• Experience with standard cell characterization and Liberty modeling, using tools such as PrimeLib, Liberate or SiliconSmart.
• Experience with library release: abstract/LEF and NDM generation, packaging and validation in P&R tools such as Innovus, Fusion Compiler or ICC2.
• Scripting in Python, Tcl, SKILL or Perl for design automation.
• Experience with EM/IR closure and low-power cells (multi-Vt, power gating, retention).
• Experience with IO/bump cell layout.
• Strong written and spoken English, and experience working in multi-site teams.

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